In this paper, we propose a hardware architecture that combines convolution and batch normalization to increase the inference accuracy of a convolutional neural network (CNN). In addition, it is implemented in the form of a module and can be applied to various CNNs. The proposed hardware architecture was implemented with Verilog-HDL, and it was confirmed that it operates normally by comparing and evaluating the output result of the reference software platform.

전성호, 옥승호. "CNN의 추론 정확도 향상을 위한 하드웨어 구조 연구." 대한전자공학회 학술대회 . (2021): 1401-1403.